ラスベガスのカジノF84B Block Diagram

Overview

The ラスベガスのカジノF84B receiver converts the four LVDS data streams back into 24bits of CMOS/TTL data with wide VCC range(2.5 to 3.6V) and falling edge clock, suited to not only mid-sized LCD panels but also security camera systems, multi-function Printers, and tablet devices.

  • LVDS to LVCMOS Conversion
  • 4chs LVDS input
    595Mbps/ch
    LVDS input skew margin ±400ps
  • LVCMOS Parallel output
    28bit/pixel
    Clock Freq. 15 to 85MHz at 3.3V
    based on Falling edge
  • Power Supply:3.3V
    ※2.5 to 3.0V available less than 70Mpixel /sec.
  • Package:TSSOP56
    ※Pin Compatible with ラスベガスのカジノF84A
  • Operating Temperature:-10 to 70℃
  • Recommended Tx:
     ラスベガスのカジノM83D
     ラスベガスのカジノM87
  • Recommended promotive replacement part
    ラスベガスのカジノF84C

Go to FAQ for this product

FAQ

Purchase Samples

Buy at Chip One Stop

Download documents