THC63LVD104C_Block Diagram

Overview

The THC63LVD104C receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104C converts the LVDS data streams back into 35bits of LVCMOS data with choice of the rising edge clock, suited to multi-function printers and security ラスベガス カジノ ルーレット systems.

  • LVDS to LVCMOS Conversion
  • 5chs LVDS input
    　784Mbps/ch
    　LVDS input skew margin ±400ps
    Failsafe Supported
  • LVCMOS Parallel output
    　35bit/pixel
    　112Mpixel/sec. (Clock Freq. 8 to 112MHz)
    　Clock reverse of data output
  • Power Supply：3.3V
  • Package：TQFP64
    　Pin Compatible with THC63LVD104A
  • Operating Temperature：-20 to 85℃
  • Recommended Tx：
    　InterfaceLVDS
    　InterfaceLVD
    　InterfaceLVDS

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